Direct Access Memory

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Direct Access Memory

 Port and Memory-Mapped I/O:


As stated earlier, the CPU communicates with the I/O controller or module to perform any input/output operating. Each controller has one or two registers that are used for communicating with the CPU. The CPU communicates with the controller by reading or writing bit patterns in these registers. The CPU can access the I/O modules by using one of the following. 

  • I/O Port 
  • Memory-Mapped I/O 

I/O Port: 

With the I/O port, the communication takes place between the CPU and the I/O module through the I/O port using special I/O instruction. The I/O address (or number) is given as a parameter to the I/O instruction. The I/O instruction trigger bus lines to select the proper device and its I/O ports and then moves bits into or out of a device register.

Memory-Mapped I/O:

Another way for communication between the CPU and the device controller is using memory-mapped I/O Each controller has a few registers that are used for communicating with the CPU. On some computers, these registers are parts of the regular memory address space. in this case, the control register is mapped into the address space of the CPU. This scheme is called memory-mapped I/O.
With memory-mapped I/O, any instruction that can access memory address space is allocated to the I/O controller. CPU executes I/O requests using the standard data transfer instruction to read and write the controller or module register.
Some systems use only approach (such as I/O port or memory-mapped I/O) other use both. 

For example:

PCs use I/O instruction to control some devices and memory-mapped I/O to control others.
Note that the port number (s) or memory address must be associated with the I/O module Permanent assignment by the manufacturer is not practical. In most cases, the port number or memory address assignment can be configured. Some of them can be configured manually using a jumper or a DIP (Dual In-line Package) switch and others using the software. In plug-and-play, the setting is made automatically by the hardware itself.

Busy Wait I/O:

Busy waiting is a loop, in which the CPU continuously tests the status registers of a module to see if the command has complete. In busy-wait I/O, the CPU waits for the completion of I/O operating and the CPU does not continue to execute another.

Communication between the I/O module and the CPU follows one of four basic protocol. In the simplest protocol, the CPU issues a command to the I/O module to start an I/O operating. In the case of output operating, CPU transfers data to the module's Data Buffer and then repeatedly checks the module to see if the command is completed successfully or not. In the case of input operating, the data is transferred from the module buffer to the CPU.

Polled I/O:

Polling is a technique of checking the status of an I/O device by CPU (or another checking units, or software). In polling I/O, the CPU starts the I/O operating required by one process and itself continues to execute another process in the system. However, the CPU returns back to the I/O module after a specific interval of time to see if the I/O operating has completed.
  • The status register holds bits that show the status of the I/O command. These bit indicate the success,
  • Polling is more efficient than the busy-wait. The wit main drawback of polling is that processes are interrupted when the CPU returns back to see the status of I\O operating. Polling is also not suitable for modules that require a fast response.

 Interrupt I/O:

Most I/O modules can also be configured for generating interrupts for I/O operating. The module generates an interrupt by putting a single on the bus and the CPU since the interrupt. For example, the I/O modules send an interrupt signal to the CPU  when I/O operating is completed. In this way, the CPU remains busy to execute other processes until the interrupt signal is received from the I/O module. This mechanism is referred to as interrupt I/O.
In Interrupt I/O the I/O operating continue and a single interrupt from the module is sent to CPU after completing the I/O operating or when aThe n error in I/O operating occurs. If the CPU is executing an instruction, it finished its execution first, before responding to the interrupt to the interrupt. The interrupt I/O improves the efficiency by providing the parallelism, but it creates complexity in complementation.

Direct Memory Access (DMA)

 Direct Memory Access (DMA) is a special hardware component, called the DMA controller. It allows the I/O module to write and read data directly to and from the main memory without the involvement of the CPU. Without DMA, its work is done through CPU.
The CPU sends requests to the DMA to perform an I/O operating such as for transferring data from the I/O device into the main memory. CPU then continue to do other tasks. In this way, data is transferred directly to the main memory by DMA without the intervention of the CPU. When the data transfer is completed, the DMA sends an interrupt signal to the CPU. Thus, the CPU is involved only at the beginning and at the end of the data transfer.
DMA scheme is particularly useful on devices like disks, where many bytes of information (or block) can be transferred in a single I/O operating. DMA needs four types of information for it's functioning.
  1. Type of commands such as Read and Write 
  2. Address of I/O device 
  3. Location of memory, where data is read from or written to 
  4. Several total bytes read from the written into the file. 

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